This invention relates to thin film transistors (TFT), in particular to TFT for use in active matrix liquid crystal display (LCD) systems.
TFTs are widely used for LCD panels. In such a TFTLCD system, each picture element (pixel) has a LCD device and a switch to turn on and off the LCD device. A matrix of pixels are placed at the cross-points of a number of rows of sequential scan signals and a number of columns of data signals. When a scan signal and a data signal is coincident at a certain cross-point, the pixel at that particular cross-point is activated. The coincident addressing of this particular pixel is accomplished by a TFT, where the scan signal may be applied to the gate of the TFT and the data signal may be impressed on the drain of the TFT and driving the corresponding LCD from the source of the TFT.
There are a number of structures for TFTs as described in a paper by M. Akiyama et al, "An a-Si TFT with a New Light-Shield Structure and Its Application to Active Matrix Liquid Crystal Displays" IEEE International Electron Devices Meeting Proceedings, Dec. 1988, pp.268-271. In general, FIGS. 1(a), 1(b) and 1(c) show the cross-sectional views of the conventional amorphous silicon (a-Si) TFTs. They are referred as type-A, type-B and type-C.
The fabrication processes of type A and type B a-Si TFTs are as follows: (1). Deposit a metal film as the gate 11 of the TFT on a transparent substrate 10. (2) Deposit a silicon nitride (a-SiN) 12, an amorphous silicon (a-Si) 13, and heavily-doped a-Si (n+ a-Si) 14 films on the substrate. (3) Etch the n+ a-Si 14 and a-Si 13 films except the active region of the TFT by the standard photolithographic and dry etching processes. (4) Form indium-tin oxide (ITO) as a transparent electrode 20 for LCD device. (5) Open the contact holes of the TFTs. (6) Form the source and drain contact metal 16 of the TFT. (7) Etch the n+ a-Si layer 14 between the source and the drain electrodes by dry etching. Because there is no etching stopper in the type A and type B TFTs, step 7 is controlled by the etching time, which is critical, and the thickness of the a-Si layer must be much thicker than that of the n+ a-Si layer 14. Typically, the thickness of the a-Si layer 13 is more than 2000 Angstroms.
Type A and type B TFTs have the same structure except that in the type A TFT, the a-Si layer protrudes beyond both edges of the gate electrode, as described by Sakamoto et al in the paper, "A 10-In.-DIAGONAL ACTIVE-MATRIX LCD ADDRESSED BY a-Si TFTs", Proceedings of the SID, Vol.28/2, 1987, pp.145-148. In the type B TFT, the a-Si layer is located completely inside the shadow of of the gate electrodes. When this device is operated in the back gate illumination condition, leakage current is observed in the type A structure, because carriers are generated in the illuminated protruded region due to photoelectric effect. Thus, the type A TFT cannot be used in the TFTLCD. For the type B structure, the a-Si layer is totally shielded by the gate electrode. Thus, there is no photocurrent when it is operated in the backside illumination condition. However, during fabrication, the a-SiN layer 12, i.e. the gate insulating layer 12, beyond the active region is attacked during the n+ a-Si and a-Si etching step (Step 3). Therefore, the yield of the type-B structure is very poor when it is used for the TFTLCD which is a matrix array of a large number of pixels.
In order to improve the yield of the TFT, an a-Si TFT which has a second layer of a-SiN 18 has been developed as shown in FIG. 1(c). The fabrication process of this type-C device is similar to that of type A and type B., except that the top nitride (a-SiN) layer is deposited after the deposition of the a-Si film and the top a-SiN layer is removed from the source and drain (S/D) contact regions before the deposition of the n+ a-Si layer. The top a-SiN layer remains in the channel region of the transistor, and can be used as the etching stopper during etching of the n+ a-Si layer between the source and drain electrodes because the a-SiN is resistant to Si etch. The thickness of the a-Si layer can be made very thin, typically less than 500 Angstroms. The a-Si layer can protrude outside both the edges of the gate electrode without incurring substantial amount of leakage current. Because the a-Si layer that protrudes outside both the edges of the gate electrode are very thin, the protruded layer absorbs very few incident photons. Since the gate insulating a-SiN layer is not attacked during the formation of the active region, the type-C device has a higher manufacturing yield than the type-B device.
In the type-A and type-B devices, the channel length is equal to the space between the source and the drain electrodes 16. In the type-C device, the channel length is equal to the length of the top a-SiN 18 and is longer than the space between the source-drain electrodes 16. Thus, if the same design rule is used, the channel length of the type-C device must be longer than that of type A or type B devices. Thus, the type C device occupies a large area, and is not suitable for high resolution displays. The detailed discussion of this effect is described in a paper by H. Katoh, "TFT-LCD Technology Achieves Color Notebook PC", Nikkei Electronics ASIA, April, pp.68-71, 1992.
In the foregoing type-A, type-B or type-C TFT, the data signal line and the source and drain electrodes are formed at the same time. There is no insulating layer between the data signal line and the ITO electrode for the pixel. Consequently, it is easy for the data signal line 17 and the ITO electrode 20 to bridge. FIG. 2 shows the top view of the pixel. If there is a bridge formed between the signal line 17 and the pixel 20 due to defective processing, the signal bypasses the TFT switch and apply directly to the pixel electrode 20. FIG. 3(A) shows the cross-sectional view along the A-A' line in FIG. 2. FIG. 3(B) shows the cross-sectional view along the B-B' line in FIG. 2. When the signal line and the pixel electrode produces a short circuit as shown in FIG. 3(B), the LCD display is impaired.
In a co-pending U.S. patent application, Ser. No. 07/875,651, filed Apr. 29, 1992, the foregoing shortcoming of prior art is overcome by adding an insulating layer on the gate before the a-Si layer is deposited. Thus, this insulating layer can be grown at a high temperature, and free from pin holes. The a-Si layer is shielded by the gate electrode to reduce the generation of leakage photo-current and to reduce the geometry of the structure. The structure also reduces the step at the interconnection crossings to avoid breakage. These effects improve the fabrication yield of the TFT LCD panels.
Although the structure disclosed in the co-pending application has substantially reduced the leakage current whet there is backside illumination, it has been found that the dark leakage current is larger than the dark leakage current of the structures with a-Si channels protruded outside the shadows of the gate electrode when negative bias is applied to the gate. This observation was described in a paper, "Leakage current of amorphous silicon thin film transistor", ROC Symposium on EDMS, p.513, 1991. In this paper, it was explained that at the edge between the a-Si and S/D electrode contact, holes flow from the a-Si/Al edge of the drain electrode to the channel region. At the edge where the a-Si is in contact with the metal, the leakage current of the TFT increases when a negative voltage is applied to the gate. The increased dark current is dominated by the trap-assisted tunneling current which is induced by the electric field of the metal/semiconductor (M/S) contact by increasing the negative gate bias or/and increasing the drain bias. The leakage current may be due to the metal precipitates into the a-Si layer in the drain edge of the a-Si layer. The metal precipitates enhance the trap state density at the contact region. Under high electric field, the electron-hole pairs are generated via the traps at the M/S contact of the drain region.
An additional shortcoming is shown in FIG. 4, which is the cross-sectional view along the C-C' line in FIG. 2. The commonly used material for reducing the resistivity of the signal line is aluminum, which is in direct contact with the pixel electrode 20, i.e. the ITO material. In FIG. 2 is shown the data signal line 17 and the scan line 19 for the TFT. When Tab Automatic Bonding technique (TAB) is used to connect these lines from the driving circuit to the top display surface, the ITO material serves as an input pad. Then, aluminum is used to connect the signal line and the scan line directly to the ITO input pads. When an aluminum and ITO contact encounters a base solution, the contact edge between the aluminum and ITO can easily be eroded as described in a paper by J. E. A. M. van den Meerakker et al."Reductive Corrosion of ITO in Contact with Al in Alkaline Solutions", J. Electrochem. Soc,,Vol.139 No.2, Feb. 1992, pp.385-390. Such base solution is commonly used to remove the photo-resist for patterning the aluminum metal. When such erosion occurs, the display becomes speckled, and, in a more serious situation, the contact between the ITO and the aluminum may become discontinuous. FIG. 4(A) shows the situation without any erosion, and FIG. 4(B) shows the situation with erosion.